In a processor that supports paged virtual memory, data may be specified using virtual (or “logical”) addresses that occupy a virtual address space of the processor. The virtual address space may typically be larger than the amount of actual physical memory in the system. The operating system in these processors may manage the physical memory in fixed size blocks called pages.
To translate virtual page addresses into physical page addresses, the processor may search page tables stored in the system memory, which may contain the address translation information. Since these searches (or “page table walks”) may involve memory accesses, unless the page table data is in a data cache, these searches may be time-consuming.
The processor may therefore perform address translation using one or more translation lookaside buffers (TLBs). A TLB is an address translation cache, i.e. a small cache that stores recent mappings from virtual addresses to physical addresses. The processor may cache the physical address in the TLB, after performing the page table search and the address translation. A TLB may commonly contain often referenced virtual page addresses, as well as the physical page address associated therewith. There may be separate TLBs for instruction addresses (instructions-TLB or I-TLB) and for data addresses (data-TLB or D-TLB).
When a TLB receives a virtual page address, the TLB may search its entries to see if the address translation information contained in any of these entries match the received virtual page address. If the virtual page address presented to a TLB does match an address translation information in any of the TLB entries, a TLB “hit” may occur; otherwise, a TLB “miss” may occur.
In response to a TLB miss, the pipeline may be stalled at the point where the miss occurs. The instruction containing the virtual address may just sit and wait, unable to proceed to the next stage because of lack of the address translation information. While this happens, all stages above the point where the miss has occurred may also have to wait, resulting in considerable inefficiency. Another measure adopted in response to a TLB miss may be to flush the instruction that missed, without stalling the instruction at a stage prior to the TLB access point. In this case, multiple misses may occur for the same instruction, requiring multiple flushes. This may also result in inefficiency.